I'm a 3rd-year CS student specializing in Computer Architecture. Last semester I had to simulate VHDL designs and the experience was painful — ancient tools, heavy GUIs, half an hour of setup just to see a waveform.

So I spent the summer building my own: a VHDL simulation engine in C++20 with a full compilation pipeline and a terminal UI debugger for cycle-accurate waveform inspection. TUIs are having a moment right now and I think hardware tooling deserves one too.

It's open source and early. Repo: https://github.com/oscar30gt/pulse — feedback and ⭐ appreciated.

Hey everyone,

I know basics of verilog and digital architecture. Have built basic projects on quartus. How can I explore this more in depth?

Thank you

Hi everyone,

Over the past few days I've been putting together a small project that I personally wanted while working on FPGA designs: a searchable collection of VHDL templates that can be copied with a single click.

The idea is simple: instead of digging through old projects or documentation every time I need a counter, FSM, synchronizer, FIFO, generate loop, RAM template, etc., I wanted a single place where I could quickly find and reuse common design patterns.

Current templates include:

• FSMs (Moore, Mealy, Safe FSMs)
• Counters and shift registers
• RAM, ROM and FIFO examples
• Synchronizers and debouncers
• Arithmetic blocks
• Structural design templates
• Testbench skeletons

It's a lightweight static website with no dependencies and works entirely in the browser.

Website: https://andrea-cpu96.github.io/vhdl-cookbook/

I'd love feedback from other FPGA/VHDL developers. Suggestions for additional templates are very welcome.

Thanks!

I posted an earlier version of this project here before. I’ve now expanded it so it can decode WDB files directly, without reopening Vivado or rerunning the simulation.

Repo : https://github.com/Ross0907/Vivado-WDB-Waveform-Converter

Main additions are direct WDB/WCFG -> VCD/CSV/JSON/Excel conversion, batch conversion, signal filtering, per-signal radix selection, SystemVerilog/VHDL + mixed-language support, and a standalone Windows executable.

AI disclosure: I used AI as a coding, reverse-engineering and debugging assistant while developing this. The decoder/output was then tested against XSim-generated reference waveforms across a fairly large set of SV/VHDL, array, real, mixed-language and stress cases.

Something interesting to note is that many times the wdb files signal naming is ambiguous so its always better to supply a WCFG file with it. Although it is possible to give those signals a random placeholder name, I choose not to have that option, but it's fully possible.

I have also done some FPGA perojects with 0.5mm pitch and non-HDI, but the SU+ Adam is using is FULL GRID, so it seems impossible to route out all pins without HDI tech. Interesting, but need to wait...

Hello everyone, I have a kind of random question. I have used both Glasgow and Cynthion for protocol debugging and reverse engineering work and they're both great, but the whole experience is python-scripting-first. No real GUI logic analyzer app, you write an applet or compose one from the cli.

I've been sketching an idea for something with the same "FPGA adapts to any protocol" flexibility, but with an actual native GUI on top, live waveforms, protocol decode, minimal setup to get a CAN/SPI/I2C/UART capture running.

Am I the only one who'd want this?

Doing 0.5mm pitch BGA FPGA boards is not impossible, but there are restrictions. I have done such a board once, I posted PCB pictures on my blog, the board used AMD Artix FPGA and BGA packaged NAND flash directly below the FPGA. The was board was manufacrured and worked well.

I am very interested about Adam Taylors Spartan Ultrascale+ escape routing, for me it seems that you can route out maximum of 3 rows of balls, the inner balls are not accessible. Well need to wait until 17 september to see how Adam did it.