I'm a 3rd-year CS student specializing in Computer Architecture. Last semester I had to simulate VHDL designs and the experience was painful — ancient tools, heavy GUIs, half an hour of setup just to see a waveform.

So I spent the summer building my own: a VHDL simulation engine in C++20 with a full compilation pipeline and a terminal UI debugger for cycle-accurate waveform inspection. TUIs are having a moment right now and I think hardware tooling deserves one too.

It's open source and early. Repo: https://github.com/oscar30gt/pulse — feedback and ⭐ appreciated.

Hi everyone,

Over the past few days I've been putting together a small project that I personally wanted while working on FPGA designs: a searchable collection of VHDL templates that can be copied with a single click.

The idea is simple: instead of digging through old projects or documentation every time I need a counter, FSM, synchronizer, FIFO, generate loop, RAM template, etc., I wanted a single place where I could quickly find and reuse common design patterns.

Current templates include:

• FSMs (Moore, Mealy, Safe FSMs)
• Counters and shift registers
• RAM, ROM and FIFO examples
• Synchronizers and debouncers
• Arithmetic blocks
• Structural design templates
• Testbench skeletons

It's a lightweight static website with no dependencies and works entirely in the browser.

Website: https://andrea-cpu96.github.io/vhdl-cookbook/

I'd love feedback from other FPGA/VHDL developers. Suggestions for additional templates are very welcome.

Thanks!

I have also done some FPGA perojects with 0.5mm pitch and non-HDI, but the SU+ Adam is using is FULL GRID, so it seems impossible to route out all pins without HDI tech. Interesting, but need to wait...

Hey everyone,

I know basics of verilog and digital architecture. Have built basic projects on quartus. How can I explore this more in depth?

Thank you

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Doing 0.5mm pitch BGA FPGA boards is not impossible, but there are restrictions. I have done such a board once, I posted PCB pictures on my blog, the board used AMD Artix FPGA and BGA packaged NAND flash directly below the FPGA. The was board was manufacrured and worked well.

I am very interested about Adam Taylors Spartan Ultrascale+ escape routing, for me it seems that you can route out maximum of 3 rows of balls, the inner balls are not accessible. Well need to wait until 17 september to see how Adam did it.

Hello everyone, I have a kind of random question. I have used both Glasgow and Cynthion for protocol debugging and reverse engineering work and they're both great, but the whole experience is python-scripting-first. No real GUI logic analyzer app, you write an applet or compose one from the cli.

I've been sketching an idea for something with the same "FPGA adapts to any protocol" flexibility, but with an actual native GUI on top, live waveforms, protocol decode, minimal setup to get a CAN/SPI/I2C/UART capture running.

Am I the only one who'd want this?

I posted an earlier version of this project here before. I’ve now expanded it so it can decode WDB files directly, without reopening Vivado or rerunning the simulation.

Repo : https://github.com/Ross0907/Vivado-WDB-Waveform-Converter

Main additions are direct WDB/WCFG -> VCD/CSV/JSON/Excel conversion, batch conversion, signal filtering, per-signal radix selection, SystemVerilog/VHDL + mixed-language support, and a standalone Windows executable.

AI disclosure: I used AI as a coding, reverse-engineering and debugging assistant while developing this. The decoder/output was then tested against XSim-generated reference waveforms across a fairly large set of SV/VHDL, array, real, mixed-language and stress cases.

Something interesting to note is that many times the wdb files signal naming is ambiguous so its always better to supply a WCFG file with it. Although it is possible to give those signals a random placeholder name, I choose not to have that option, but it's fully possible.

A practical PS/PL partitioning pattern is to keep fast deterministic processing in PL and interrupt the processor only when software involvement is required.

I implemented this on a ZCU104 with ADC acquisition, moving-average filtering, hysteresis, control logic and PWM in PL. Threshold transitions generate a sticky interrupt through the GIC to the Cortex-A53.

Physical validation showed repeated ACTIVE/INACTIVE transitions with the FPGA event counter matching the ISR count, confirming correct interrupt servicing and re-arming.

https://github.com/franksombudsman-ops/fpga-rtl-portfolio/tree/feat/zcu104-interrupt-driven-soc-control/projects/zcu104/04-interrupt-driven-soc-control

After I run an implementation in Vivado, I usually generate the timing, critical paths, and utilization reports as .rpt files and look through them. They can be a bit dense sometimes though, so I was wondering if anyone knew of open-source/free tools or tcl scripts that are out there to process these reports and make them a little easier to digest quickly?

I’m trying to get a Red Pitaya Gen 2 board an IP address via DHCP and I’m stuck. Hoping someone with more experience can spot what I’m missing.

Setup:
• Red Pitaya Gen 2, connected by Ethernet
• Accessing the board over a serial console
• OS uses systemd-networkd

What I’ve checked so far:
• /etc/systemd/network/wired.network looks correct: DHCP=yes, [Match] Name=eth0
• Interface name matches (eth0), MAC looks fine
• systemd-networkd is now active
• Link/physical layer, interface state, and ARP to the other end all pass

Hi, does anyone have any advice on how to prep for this, what might be tested etc? Thanks

Hello everyone,

I am a Mathematics and Computer Science student in the Netherlands. I managed to secure a one year placement at a semiconductor company here although as an AI Intern. I’m also graduating later this year, so very soon apart from the placement I won’t be going to school. After the placement I plan on doing my master’s and in the future I would love to return as an FPGA Engineering Intern. I have a class on Digital Design and Computer Architecture this semester and I’m wondering how to best support my learning and what topics are of importance in particular, and what resources I can use. For instance, how do I learn high speed networking on hardware? Ethernet? I have had a networking class but it was a general overview.

Thanks in advance.

i m in college , btech 3rd year ece , i wanna buy a fpga board for my learning experince and i dont wanna buy expensive fpga board. my budget is under 5k and i have found 2 fpga board that is tang nano 9k and altera cyclone II , for tang nano i cn use yosys and growin eda but i dont like growin eda bcs its asking way mush information to download a software and also its a chinise origin makes me hesitate a little , so i m thinking i should go with altera cyclone II but where to buy it from , amazon or robuin

Ran as admin too, WIndows 11 25H2. No other error came up other than this. Same errors on both SFD and its dedicated installer, even reinstalled VC+++ but nothing changes, can't put my license in the license manager, please suggest

Last week I decided to continue one of my ongoing side projects: A VCD viewer directly in the terminal.

Mostly because I was fed up with the strange UX/UI of traditional tools like QuestaSim or GTKWave. Im not saying my "fuck this shit, im doing it myself" approach resulted in something actually better, but it does look quite cool in my opinion.

Its available here, but keep in mind that it only works with Linux and does not support all VCD features.

Hello everyone,

I am a Mathematics and Computer Science student in the Netherlands. I managed to secure a one year placement at a semiconductor company here although as an AI Intern. I’m also graduating later this year, so very soon apart from the placement I won’t be going to school. After the placement I plan on doing my master’s and in the future I would love to return as an FPGA Engineering Intern. I have a class on Digital Design and Computer Architecture this semester and I’m wondering how to best support my learning and what topics are of importance in particular, and what resources I can use. For instance, how do I learn high speed networking on hardware? Ethernet? I have had a networking class but it was a general overview.

Thanks in advance.

Hi, this was my attempt at a problem I had faced where sometimes I want to export the vcd generated by vivado to other formats, this script and python file does exactly that. Please have a look and let me know about any shortfalls or missing features thiar you'd like to be added. Feel free to open pull requests.

Ps. AI was used to making this , I have not fully coded this myself.

Background: I have a Master's in EEE from a Russell Group university.

I'm looking for graduate/entry-level FPGA jobs but trying to completely avoid defense companies. I know this is a topic of debate, but that's not the reason for my post.

I want to know: if I'm not keen on working in the defence industry, am I limiting myself to a point where it's better to change career paths because of how hard it is to find an entry-level FPGA job elsewhere?

I released Veryl 0.21.0.

Veryl is a modern hardware description language as alternative to SystemVerilog. This version focuses on portability across targets and on using components from other projects.

• Explicit opt-in for constructs which are valid on FPGA but not on ASIC, and a policy for accepting them from dependencies
• Component namespace import to reference a package, module, interface or project scope function of a dependency by its own name
• Generic arguments of a function call inferred from module ports
• Combinational loop analysis rebuilt on sparse SSA, without the array size limit

Please see the release blog for the detailed information:

https://veryl-lang.org/blog/announcing-veryl-0-21-0/

• Website: https://veryl-lang.org/
• GitHub : https://github.com/veryl-lang/veryl
• Discord: https://discord.com/invite/MJZr9NufTT

Bought a CrossLink-NX board from Mouser.

Trying to get a license to use Radiant and the lattice site just seems broken. Coming from Vivado/Vitis.

Anyone else having issues or had issues?